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Chapter 03 · Part VI · Modern Physics
Revised on ____________________
Chapter 03 · Semiconductor Electronics

One small gap, and everything downstream of it

2 sheets
2 diagrams
26 results

Formulas and conditions only — no derivations, no solved numbers. The diagrams are the reader's own.

I

Bands and doping

DOPING ADDS CARRIERS, NOT CHARGE
I.Band gap  conductor ≈ 0, semiconductor ≈ 1 eV, insulator > 3 eV
II.Silicon / germanium  Eg = 1.1 eV , 0.7 eV
III.Conductivity  σ = e (ne μe + nh μh)
IV.With temperature  n ∝ e−Eg/2kBT resistance falls on heating
V.Mass action  ne nh = ni² at a given temperature
VI.n-type  pentavalent donor — P, As, Sb electrons major, holes minor
VII.p-type  trivalent acceptor — B, Al, In holes major
VIII.Both types  electrically neutral each donor leaves a fixed positive ion
II

The p–n junction

A DROP, NOT A BATTERY
I.Depletion region  immobile ions, no free carriers 0.5 µm or so
II.Barrier potential  0.7 V (Si), 0.3 V (Ge)
III.Forward bias  barrier lowered, width shrinks, current rises steeply
IV.Reverse bias  barrier raised — only a µA leakage
V.Diode equation  I = I0 ( eeV/kBT − 1 )
VI.In a circuit  I = Vsupply − 0.7R never V/R, never 0.7/R
the one-way valve, drawnnothing much until the knee · then almost a short circuitVIbreakdown−I₀ (µA, and flat)knee ≈ 0.7 V (Si)0.3 V for Geforward: mA, steepreverseI = I₀ [ exp(eV / kBT) − 1 ]dynamic resistance rd = VT / I — not a constant
III

Rectifiers and regulation

FULL WAVE RIPPLES AT 2f
I.Half-wave output  ripple at f ηmax = 40.6 %
II.Full-wave / bridge  ripple at 2 f ηmax = 81.2 %
III.Peak inverse voltage  bridge Vm, centre-tap 2Vm
IV.Zener  operated in reverse breakdown V across the load stays at VZ
V.Series resistor  Rs = Vin − VZIZ + IL
VI.Photodiode / LED / solar cell  reverse, forward, and unbiased junctions
IV

Logic gates

TWO INPUTS, EIGHT ANSWERS
I.OR  Y = A + B
II.AND  Y = A · B
III.NOT  Y = A
IV.NAND  Y = A · B universal — builds any gate
V.NOR  Y = A + B also universal
VI.XOR  Y = A B + A B 1 when the inputs differ
Si gap
1.1 eV
Si drop
0.7 V
Ge drop
0.3 V
Full-wave ripple
100 Hz from 50 Hz
Bridge PIV
Vm
Centre-tap PIV
2Vm
the digital layer: five gates, and one of them is enoughNAND or NOR alone can build every other gate — and therefore any computerABYORY = A + BA B Y0 0 00 1 11 0 11 1 1ABYANDY = A · BA B Y0 0 00 1 01 0 01 1 1AYNOTY = A′A Y0 11 0ABYNANDY = (A · B)′A B Y0 0 10 1 11 0 11 1 0ABYNORY = (A + B)′A B Y0 0 10 1 01 0 01 1 0UniversalNOT = NAND, inputs tiedAND = NAND then NOTOR = NAND on both inverted inputs
V

Where the marks go

FOUR ERRORS, EVERY YEAR
Where marks are lost in this chapter
1Expecting a semiconductor to behave like a weak metal. Its resistance falls as the temperature rises.
2Calling n-type silicon negatively charged. Each donor leaves a fixed positive ion — the material is neutral.
3Reading the 0.7 V drop as a source. The external circuit sets the current: I = (Vsupply − 0.7)/R.
4Using the mains frequency as the ripple frequency. A full-wave rectifier ripples at 2f.